Mobile devices or systems, such as but not limited to personal data appliances, cellular phones, radios, pagers, lap top computers, and the like are required to operate for relatively long periods before being recharged. These mobile devices usually include one or more processors as well as multiple memory modules and other peripheral systems.
The power consumption of a transistor-based system is highly influenced by leakage currents that flow through the transistor. The leakage current is responsive to various parameters including the threshold voltage (Vt) of the transistor, the temperature of the transistor, supply voltage and the like. Transistors that have higher Vt are relatively slower but have lower leakage currents while transistors that have lower Vt are relatively faster but have higher leakage current.
In order to reduce the power consumption of mobile systems various power consumption control techniques were suggested. A first technique includes reducing the clock frequency of the mobile system. A second technique is known as dynamic voltage scaling (DVS) or alternatively is known as dynamic voltage and frequency scaling (DVFS) and includes altering the voltage that is supplied to a processor as well as altering the frequency of a clock signal that is provided to the processor in response to the computational load demands (also referred to as throughput) of the processor. Higher voltage levels are associated with higher operating frequencies and higher computational load but are also associated with higher energy consumption.
A third technique uses domino circuits that include both high threshold voltage transistors and low threshold voltage transistors. U.S. patent application number 2004/0008056 of Kursun et al., which is incorporated herein by reference, discloses a domino circuit that is configured such as to reduce power consumption, for example by limiting the energy consumed during power switching.
Yet another technique is based upon creating a stack effect that involves shutting down multiple transistors of the same type that are serially connected to each other. U.S. Pat. No. 6,169,419 of De et al., which is incorporated herein by reference, discloses a method and apparatus for reducing standby leakage current using a transistor stack effect. De describes a logic that has both a pull up path and a pull down path.
In some prior art systems data is stored in data retention circuits while other parts of the system are shut down. The following patents and patent applications, all being incorporated herein by reference, provide a brief overview of prior art retention circuits: U.S. patent application publication number 2004/0051574 of Ko et al; PCT patent application publication number WO 2004/021351A1 of Garg et al; U.S. Pat. No. 5,600,588 of Kawashima; U.S. patent application 2004/0227542 of Bhavnagarwala et al. and U.S. Pat. No. 6,755,180 of Biyani et al.
There is a growing need to find effective systems and methods for reducing power consumption of integrated circuits.